Integrated test circuit arrangement and test method

ABSTRACT

An integrated test circuit arrangement is provided that contains integrated test structures, at least one integrated heating element, an integrated detection unit, an integrated supply unit, and a control unit. The integrated detection unit detects at least one physical property for each of the test structures. The integrated supply unit supplies each of the test structures with a current or a voltage in switchable fashion independently of one another. The control unit is connected to outputs of the detection unit on an input side and controls the supply unit dependent on the detection results.

The invention relates to an integrated test circuit arrangementcontaining a multiplicity of test structures.

Test structures that are subjected to reliability tests, by way ofexample, are or contains inter alia dielectrics, metallizations orelectronic components, in particular integrated components. In order toaccelerate the test, it is possible, on the one hand, to use for examplehigher temperatures, higher currents and/or higher voltages duringtesting and during normal operation of the arrangement to be tested. Onthe other hand, it is possible to achieve for example acceptably shorttest durations by the structures to be tested not being tested untilfailure, but rather only until a specific limit value is reached.

It is an object of the invention to specify, for testing electronic teststructures, a circuit arrangement constructed in a simple manner which,in particular, enables testing in an environment that is as simple aspossible and with the fewest possible interventions by operatingpersonnel. Moreover, the intention is to specify a test method.

The object relating to the circuit arrangement is achieved by means of acircuit arrangement having the features specified in patent claim 1.Developments are specified in the subclaims.

The invention is based on the consideration that it is possible tointegrate many of the devices required for a reliability test in thetest circuit arrangement, so that these devices do not have to beseparately procured, maintained and operated.

Therefore, the test circuit arrangement according to the inventioncontains, besides the test structures, at least one heating elementand/or at least one detection unit and/or at least one supply unit. Theheating element serves for heating the test structures to a temperaturerequired for the reliability test, which temperature is usuallyconsiderably greater than the room temperature of the room in which thetest is carried out. For each test structure, the detection unit detectsa physical quantity established on account of the heating and, ifappropriate, on account of additional measures at the test structure,for example the resistance thereof or the leakage current thereof.

The use of the test circuit arrangement with an integrated heatingelement makes it possible to carry out the reliability tests withoutusing a thermal cabinet. It would be necessary to fix the devices withthe test structures on circuit boards into the thermal cabinet and loadthem in each case by a dedicated current or voltage source. Such thermalcabinets would only be required in small numbers, and so they would bevery expensive to produce. At test temperatures of, for example, greaterthan two hundred degrees Celsius or even greater than three hundreddegrees Celsius, it would be necessary to satisfy particularrequirements made of a stable contact between the device, the circuitboard or between the circuit board and the connections. This wouldresult in very expensive circuit boards which, moreover, would only havea very limited service life at the test temperatures mentioned, forexample of just a thousand test hours.

In one development of the circuit arrangement according to theinvention, test structures of a group have the same construction. Thesame construction is the basis for a reliable comparison result. By wayof example, all the test structures of a group comprise:

-   -   interconnects which preferably contain a metal or comprise a        metal, and/or which are in each case led into another        metallization layer or metallization plane by means of at least        one via or contact hole which particularly influences the        reliability,    -   dielectric layers to which a test voltage is applied, or    -   electronic components, e.g. active electronic components such as        transistors or passive electronic components such as capacitors,        resistors or coils.

In another development, test structures of different groups areintegrated into the test circuit arrangement, for example a group withvia interconnects, a group with dielectrics and a group with activeelectronic components. Separate thermal cabinets would be required forthe tests of such different groups since different test requirementsexist.

In a next development with a test circuit arrangement containingdifferent groups of test structures, the test structures of differentgroups are integrated spatially, i.e. in different planes parallel tothe plane of a carrier substrate for the test structures. These measuresenable a multiplicity of test structures to be arranged and tested evenwhen the integrated circuit arrangement has a very small area. By way ofexample, so-called via 1 structures could be arranged below so-calledMIM capacitor structures (Metal Insulator Metal).

In a next development, a group of test structures contains more thanfifty, more than one hundred or even more than a thousand teststructures. The statistical meaningfulness of the test results increasesconsiderably as the number of test structures increases. Very many teststructures can be integrated into the test circuit arrangement without ahigh additional outlay in terms of process engineering. The test ofthese structures likewise requires no or at any rate only comparativelylittle additional outlay.

In a next development of the circuit arrangement according to theinvention, the heating element is a resistance heating element whichpreferably contains polycrystalline silicon or comprises polycrystallinesilicon. In order to set the conductivity of the polycrystallinesilicon, it is doped. However, other developments also make use ofheating elements which contain a metal or comprise a metal. If theheating element is fed with AC current, then it is possible to preventor considerably reduce degradation processes, e.g. electromigration inparticular in heating elements made of metal.

In one development, a supply unit is also integrated into the testcircuit arrangement. The supply unit contains for example a multiplicityof voltage sources or of current sources. In one configuration, thesupply unit supplies the test structures with a current or a voltageindependently of one another. An independent supply makes it possible toterminate the test of one test structure despite continuing a test atother identically constructed test structures of the circuit arrangementbefore the test structure fails. In addition, the material is availableafter the conclusion of the test for material examinations in a state atwhich a failure criterion was just fulfilled.

In a next development, the heating element has a straight profile or ameandering profile. Heating elements with a triangular function profile,i.e. a zigzag profile, or with a rectangular function profile are alsoused.

In another development, the supply unit contains a plurality of currentsources or a plurality of voltage sources. In particular current sourcescontaining a plurality of current mirrors can be integrated in aparticularly simple manner. On the basis of the choice of the areas ofthe transistors contained in a current mirror, currents which are amultiple or a faction of a reference current, for example an integralmultiple or a faction of integral values, can be generated in aparticularly simple manner.

In a next development, the detection unit is connected to each teststructure or can be connected to each test structure. The detection unitcontains at least one counter unit, which is clocked in accordance witha predetermined clock. A detection unit constructed in this way candetect physical properties at individual test structures and determinethe detection instant with the aid of the counter unit. By way ofexample, the counter unit could be an electronic clock.

In another development, the detection unit contains at least onemultiplex unit, the inputs of which are electrically connected to arespective test structure. The use of a multiplex unit makes it possibleto utilize assemblies of the detection unit successively for a pluralityof test structures. Thus, in a next development, the output of themultiplex unit is connected to the input of a comparison unit, the inputof which is electrically connected to a reference structure. Thereference structure has for example a different construction and/ordifferent dimensions than the test structure. What is achieved by meansof this development is that a multiplicity of test structures can betested with a comparison unit. The error or failure criterion of a teststructure is predefined by the reference structure.

In a next development, the circuit arrangement contains a control unit,which is connected to the outputs of the detection unit on the inputside. The control unit for example outputs detection results and/ordrives the supply unit in a manner dependent on the detection results.By way of example, if the failure criterion is generated by a teststructure, then the current source or the voltage source for this teststructure is switched off. This measure ensures that the test structurecan be examined later with the aid of material examining methods, thestate when meeting the failure criterion being preserved.

In another development, the control unit additionally outputs a datumfor ascertaining the detection time and a datum for identifying aspecific test structure in a manner dependent on a detection result forthis test structure. When the data are in a fixedly predefined order,identifiers for the test structures are not absolutely necessary becausethe position of a test datum in the order specifies the test structureassociated with this test datum. What is thus achieved through the useof the control unit is that the circuit arrangement can output a set ofresults for all the test structures examined in digital form. As aresult, the tests can be carried out with low complexity,cost-effectively and for large numbers. The area of the integratedcircuit arrangement that is required for the control unit and for thedetection unit is more than compensated for by the saving of amultiplicity of connection pads.

In another development, the circuit arrangement contains a substrate,for example made of a semiconductor, in particular made of silicon. Thetest structures, the heating element, the detection unit and, ifappropriate, also the supply unit and/or the control unit are arrangedin the substrate or in a manner mechanically fixed to the substrate. Toput it another way, the individual parts of the circuit arrangementcannot be released from the substrate without said circuit arrangementbeing destroyed, in particular not by means of mechanical tools ormanually, as would be the case with thermal cabinets.

In a next development, the test circuit arrangement is arranged in aplastic housing or in a ceramic housing. On account of the integrationof the heating element, plastic housings can still be used even attemperatures of above two hundred degrees Celsius.

The invention additionally relates to a test method for testing teststructures, in which the following steps are implemented withoutlimitation by the order specified:

-   -   integration of test structures into an integrated circuit        arrangement,    -   integration of at least one detection unit and/or a supply unit        into the integrated circuit arrangement,    -   connection of the test structures to the supply unit,    -   detection in each case of at least one physical property of the        test structures by means of the detection unit.

The use of an integrated heating element makes it possible, in onedevelopment or in another aspect, for example to implement reliabilitytests without using a complex test apparatus, for example without usinga thermal cabinet.

In another development, the heating element is heated to temperatures ofgreater than two hundred degrees Celsius or greater than three hundreddegrees Celsius. Despite these high temperatures, only a low heatingpower is required because only the volume occupied by the circuitarrangement or even only a part of said volume has to be heated, but notthe comparatively large volume of a heating cabinet.

In another development, output electronics integrated into theintegrated circuit arrangement output a set of result data for all thetest structures. The outputting of a set of result data with apredefined data structure gives rise to an interface that permitsoperation of the test circuit arrangement independently of units for thecomplete evaluation of the result data.

Exemplary embodiments of the invention are explained below withreference to the accompanying drawings, in which:

FIG. 1 shows the division of the area of an integrated test circuitarrangement between different functional units, and

FIG. 2 shows a basic illustration of the inter-connection of functionalunits for the test of a group of test structures.

FIG. 1 shows an integrated test circuit arrangement 10 arranged forexample on a square silicon chip having edge lengths L that are smallerthan ten millimeters. A connection region 14 containing a plurality ofconnections 16 to 26 that are electrically insulated from one another isarranged along an edge 12. The function of the connections 16 to 26 isexplained in more detail below with reference to FIG. 2.

Three test structure groups T1 to T3 extend along an edge 30 of thecircuit arrangement 10 that adjoins the edge 12. Two further teststructure groups T4 and T5 are situated along an edge 32 opposite theedge 30. The test structure groups T1 to T5 occupy approximatelyidentical areas in the exemplary embodiment. The test structure group T1contains metallic via interconnects, by way of example. The teststructure group T2 contains dielectrics by way of example.

An evaluation circuit 34 and a timer unit 36, the functions of which isexplained in more detail below with reference to FIG. 2, areadditionally situated between the test structure group T4 and theconnection region 14. Moreover, in the integrated circuit arrangement10, there are additionally a multiplicity of current sources and voltagesources 40 and a plurality of comparators 42 in a central region betweenthe test structure groups T1 to T3, on the one hand, and the teststructure groups T4 and T5, on the other hand. The voltage sources arerequired for the test of the dielectrics, by way of example. In anotherexemplary embodiment, only current sources 40 or only voltage sources 40are utilized.

In the exemplary embodiment explained, there are no further assembliessituated in the circuit arrangement 10, in particular no user circuitsbesides the test circuit.

In another exemplary embodiment, by contrast, the circuit arrangement 10contains components of a user circuit, see dashed line 50. The usercircuit is for example a memory unit having several million memory cellsor a processor. In this exemplary embodiment, the reliability tests arecarried out on structures that have been fabricated by means of the sameprocesses as identical structures in the user circuit. With such anintegrated circuit, ongoing production can be monitored in the manner ofrandom sampling or in its entirety in a very reliable manner.

FIG. 2 shows a basic illustration of the combination of functional unitsof the integrated circuit arrangement 10. These functional units includea multiplicity of current sources 60 to 68, which form a part of thecurrent/voltage sources 40.

A heating element 70 lies below test interconnects 80 to 86 having thesame construction and below a reference interconnect 88, which has thesame construction as the test interconnects 80 to 86 but is twentypercent longer than the interconnects 80 to 86. The test interconnects80 to 86 form the test structures of the test structure group T1. Thereare connecting interconnects 90 to 98 in each case between the currentsources 60 to 68 at one end and the test interconnects 80 to 86 and alsothe reference interconnect 88 at the other end. The connectinginterconnect 98 is shown dashed in FIG. 2 since the current source 68feeds a current into the reference interconnect 88 during the test onlywhen the reference interconnect 88 is used for a comparison with one ofthe test interconnects 80 to 86.

At the other end the current sources 60 to 68 are also connected to aground line M which leads, with the interposition of a resistor, by wayof example, to the other ends of the test interconnects 80 to 86 and tothe other end of the reference interconnect 88, see arrow 100.

The current sources 60 to 68 are realized with the aid of currentmirrors which duplicate a reference current impressed via the connection16. In addition, the current sources 60 to 68, as explained in moredetail below, can be individually switched on and switched off.

The heating element 70 is supplied with an AC current, by way ofexample, via the connections 18 and 20. A resistance contained in theheating element 70 has a meandering profile.

The ends of the interconnects 80 to 86 which are not connected to thecurrent sources 60 to 68 are connected to the inputs of a multiplexer102. By way of example, the multiplexer 102 has two hundred input lines110 to 116. The output of the multiplexer 102 is connected to thenoninverting input of a comparator 42 a that is associated with thecomparators 42. The inverting input of the comparator 42 a is connectedto that end of the reference interconnect 88 which is not connected tothe current source 68, see arrow 120.

The control inputs of the multiplexer 102 are connected to the outputsof a counting unit 130. The counting unit 130 counts for examplecyclically from one to two hundred, see arrow 132.

The output of the comparator 42 a leads to the evaluation circuit 34,see connecting interconnect 140. The output of the evaluation circuit 34is connected to the connection 26. The evaluation circuit 34 accessesthe counter value of the counting unit 130 and the timer unit 86, whichis realized by a further counter in the exemplary embodiment, see arrows150 and 152. An arrow 160 symbolizes the control function of theevaluation circuit 34 with regard to the current sources 60 to 68.

The timer unit 36 and the counter unit 130 are clocked by a clock Tpresent at the connection 24. By way of example, the clock T has a clockperiod of ten milliseconds.

In order to test the interconnects 80 to 86 for reliability or in orderto determine the life time, for example with regard to electromigration,at the beginning of the test the current sources 60 to 66 are switchedon, so that they in each case feed a constant current into the testinterconnects 80 to 86. An AC voltage is applied to the heating element70 and then a constant temperature of two hundred and fifty degreesCelsius, for example, is generated at the test interconnects 80 to 86and also at the reference interconnect 88 with the aid of a temperatureregulating circuit. With each clock pulse of the clock T, the countervalue of the counter unit 130 is incremented by the value one. As aresult, a voltage is successively tapped off at the interconnects 80 to86 and compared with the voltage tapped off at the referenceinterconnect 88 in the comparator 42 a. In order to restrict theelectromigration in the reference interconnect 88, the constant-currentsource 68 is switched off again between the individual comparisons.

As soon as a voltage signal that signals an identical voltage value atboth inputs of the comparator 42 a or a larger voltage value at thenoninverting input of the comparator 42 a occurs at the output of thecomparator 42 a or on the connecting line 140, the evaluating circuit 34reads the counter reading in the counter unit 130. Said counter readingindicates that test interconnect 80 to 86 at which a voltage iscurrently being tapped off. The counter reading that has been read isrecorded in a memory unit (not illustrated) of the evaluation circuit orgives serves for determining a memory location for storing a resultdatum. In addition, the evaluation circuit 34 accesses the counter valueof the timer circuit 36. The value is read and stored together with thecounter value of the counter unit 130 in the memory unit or at thememory location determined. The counter value of the timer unit 36indicates the detection instant at which the voltage was tapped off atthe relevant interconnect 80 to 86. As an alternative, the detectioninstant can be determined with the aid of the counter value of the timerunit 36.

In addition, in the case where the voltages at the input of thecomparator 42 a are identical, the evaluation circuit 34 causes thatcurrent source 60 to 66 to be switched off which leads to aninterconnect 80 to 86 at which a voltage is currently being tapped off.As a result, a multiple recording of counter readings for a testinterconnect 80 to 86 is also avoided. By way of example, the counterreading of the counter unit 130 can again be used for determining theinterconnect 80 to 86.

If all the current sources 60 to 66 have been switched off successivelyor if a predefined value has been reached in the timer unit 36, then theevaluation unit 34 outputs a set of detection data at the connection 26.By way of example, a data processing system is connected to theconnection 26 and is used to represent the detection data on a displayunit. The data can also be stored with the aid of the data processingsystem for later evaluations.

In another exemplary embodiment, just a single counter is used in placeof the timer unit 36 and the counter unit 130. The most significantdigits of the counter value are passed to the multiplexer 102 via a databus, see arrow 132. In this way, the inputs of the multiplexer 102 thatlead to the interconnects 80 to 86 are again cyclically connected to theoutput of the multiplexer 102. The evaluation circuit 34 needs to readonly one counter value in this case. It is possible to determine fromthis counter value both the detection time and that of the testinterconnect 80 to 86 at which a voltage was tapped off at the detectioninstant.

If, as explained in the exemplary embodiment, the reference interconnecthas a length that is twenty percent greater than the length of the testinterconnects 80 to 86, then the nonreactive resistance of the referenceinterconnect 88 is also twenty percent greater than the nonreactiveresistance of an inter-connect 80 to 86. The failure criterionpredefined by the reference interconnect 88 consists in terminating thetest of a test interconnect 80 to 86 if the resistance of a testinterconnect 80 to 86 has increased by twenty percent. This means inother words that the change dR in the resistance R of an interconnect 80amounts to twenty percent of the original resistance R at the start ofthe test, i.e. dR/R=20%. Other values for the failure criterion or elseother failure criteria can be predefined in an analogous way.

1. An integrated test circuit arrangement having integrated teststructures, at least one integrated heating element, an integrateddetection unit, which detects at least one physical property for each ofthe test structures, an integrated supply unit, which supplies each ofthe test structures with a current or a voltage in switchable fashionindependently of one another, and a control unit which is connected tooutputs of the detection unit on an input side and which controls thesupply unit dependent on the detection results.
 2. (canceled)
 3. Thecircuit arrangement as claimed in claim 1, wherein the test structuresof a first group have the same construction among one another.
 4. Thecircuit arrangement as claimed in claim 1, wherein at least one of: thesupply unit contains at least one of: a multiplicity of integratedcurrent sources and a multiplicity of integrated voltage sources, andthe current sources contain a plurality of current mirrors which eachgenerate a multiple or a fraction of a reference current or a currenthaving the magnitude of the reference current.
 5. The circuitarrangement as claimed in claim 2, wherein the heating element at leastone of: contains a resistance heating element which comprisesmonocrystalline silicon or polycrystalline silicon or which comprises ametal, and has a straight profile, a meandering profile, a triangularfunction profile or a rectangular function profile.
 6. The circuitarrangement as claimed in claim 1, further comprising at least onereference structure, at least one of the construction and the dimensionsof which differ from the construction and the dimensions of the teststructures.
 7. The circuit arrangement as claimed in claim 1, whereinthe detection unit at least one of: is connected or can be connected tothe test structures, and contains at least one counter unit, which isclocked in accordance with a predetermined clock.
 8. The circuitarrangement as claimed in claim 1, wherein at least one of: thedetection unit contains at least one multiplexer unit, the inputs ofwhich are electrically connected to a respective test structure, and anoutput of the multiplexer unit is connected to a first input of acomparison unit, a second input of which is electrically connected to areference structure, the reference structure having at least one of adifferent construction and different dimensions than the teststructures.
 9. The circuit arrangement as claimed in claim 1, whereinthe control outputs at least one of: detection results, a datum forascertaining the detection instant and datum for identifying the teststructures.
 10. (canceled)
 11. The circuit arrangement as claimed inclaim 1, further comprising electronic components associated with a usercircuit.
 12. The circuit arrangement as claimed in claim 1, wherein thecircuit arrangement is encapsulated in a plastic housing or in a ceramichousing.
 13. A method for testing test structures, the method comprisingthe following steps that are implemented without limitation by the orderspecified: integrating test structures into an integrated circuitarrangement, integrating a detection unit into the integrated circuitarrangement, the detection unit detecting at least one physical propertyof the test structures, integrating at least a part of a supply unitinto the integrated circuit arrangement, connecting the test structuresto the supply unit, detecting one of the physical properties of each ofthe test structures by means of the detection unit, and integrating acontrol unit into the integrated circuit arrangement, which is connectedto outputs of the detection unit on an input side and which controls thesupply unit dependent on the detection results.
 14. The method asclaimed in claim 13, further comprising at least one of the followingsteps: integrating at least one heating element into the integratedcircuit arrangement, warming or heating the test structures with the aidof the heating element, and connecting the supply unit to the teststructure during warming or during heating. 15-16. (canceled)
 17. Themethod as claimed in claim 13 further comprising the following steps:integrating at least one reference structure, at least one of theconstruction and the dimensions of which differ from the constructionand the dimensions of the test structures, detecting one of the physicalreference properties at the reference structure, comparing the one ofthe physical properties with a reference property or comparing aquantity generated from the one of the physical properties and aquantity generated from the reference property.
 18. The method asclaimed in claim 13, wherein the same physical properties of differenttest structures are successively compared with a reference property. 19.The method as claimed in wherein the heating element is at least one of:fed with at least one of an AC current and a DC current, and heated totemperatures of greater than two hundred degrees Celsius.
 20. The methodas claimed in claim 13, wherein an output circuit is integrated into theintegrated circuit arrangement, the output circuit outputs at least oneset of detection data for the test structures.
 21. The method as claimedin claim 13, wherein the method is implemented at least one of: with anunencapsulated integrated circuit arrangement, with an integratedcircuit arrangement that is still arranged on a semiconductor wafer, thesemiconductor wafer carrying a multiplicity of other integrated circuitarrangements, and for the purpose of monitoring ongoing production. 22.The method as claimed in claim 13, further comprising integrating atleast a part of the supply unit into the integrated circuit arrangement,said part containing at least one active component.
 23. The circuitarrangement as claimed in claim 2, wherein: the test structures of asecond group contain interconnects which at least one of: comprise ametal or are led into another metallization layer by means of a via, thetest structures of a third group contain dielectrics, or the teststructures of a fourth group contain active or passive electroniccomponents.
 24. The circuit arrangement as claimed in claim 11, whereinthe electronic components comprise at least one of a memory unit and aprocessor.
 25. The method as claimed in claim 17, further comprisingregistering an instant at which the comparison result changes.